Pulsewidth Control with Delay Locked Loop
نویسندگان
چکیده
The duty-cycle of a clock, within the VLSI IC, is liable to be changed when the clock passes through several buffer stages in the multistage clock buffer design. The pulse-width may be changed due to unbalance of the p and n MOS transistors in the long CMOS buffer. This paper describes a delay locked loop with double edge synchronization mainly used in a clock alignment process. SPICE simulation results, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50±0.8)% within the operating frequency range, from 55 MHz up to 166 MHz.
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